The invention relates to an information processing apparatus in which high reliability is required for a processor.
FIG. 7 is a general bus coupling type multi-processor. In the figure, 1-1, 1-2 and 1-n are processor modules. 2 is a shared memory. 3 is an I/O controller. 4 is a system bus for coupling these devices. The processor module 1-n generally uses the shared memory 2 and the I/O controller 3 via the system bus 4. Therefore if a fault occurs in any processor module 1-n, then the shared memory 2 is inoperative and also the system is apt to break down. Accordingly it is necessary to detect faults of the processor module.
FIG. 8 is a block diagram of the processor module in the conventional information processing apparatus disclosed in the U.S. Pat. No. 4,541,094. In the figure, processor module 1 is comprised of the boards 1a and 1b of the same construction. In the boards 1a and 1b, 10a and 10b are processors which operate in the same way. 11a and 11b are memories for storing the data. 12a and 12b are bus interfaces which transfer the data between internal buses 17a, 17b and the system bus 4. 13a and 13b are comparators which detect and compare the signals of the internal buses 17a and 17b. 14a and 14b are buffers which connect the processor buses 16a, 16b with the comparator 13b, 13a, respectively. 15a and 15b are buffers which connect the processor buses 16a, 16b with the internal buses 17a, 17b, respectively. 18a and 18b are buffers which connect the outputs of the processor buses 16a, 16b and the buffers 14b, 14a, respectively. Memories 11a and 11b are half memories which logically consist of one memory by the two.
The operation of the information processor of FIG. 8 is explained here. When the processors 10a and 10b read out the data from the memories 11a and 11b, respectively, the processors 10a and 10b send the address data to the processor buses 16a and 16b, respectively. The memories 11a and 11b and comparators 13a and 13b receive this data and the comparators 13a and 13b compare the address data with other address data received from the other boards via the buffers 14b and 14a, respectively. When the address sent from the processors 10a and 10b indicates the memory 11a side, the memory 11a sends the data to the processor 10a via the buffer 15a and also sends the data to the processor 10b via the buffers 14a and 18b. When the address sent from the processors 10a and 10b indicates the memory 11b side, the memory 11b sends the data to the processor 10a via the buffer 14b and 18a and also sends the data to the processor 10b via the buffers 15b. When the processors 10a and 10b write the data into the memories 11a and 11b, the address data are sent in the same way as that of reading the data. When the data sent from the processors 10a and 10b indicates memory 11a side, the processors 10a and 10b send the data to the processor buses 16a and 16b, respectively. The memory 11a receives the data via the buffer 15a, and the comparator 13a compares the data received via the buffers 14a with the data received from the processor 10a, and the comparator 13b compares the data received via the buffers 14b with the data received from the processor 10b, and they detect errors. When the data accessed from the processors 10a and 10b are not in the memories 11a and 11b, the addresses and the data are sent to the shared memory 2 via the system bus 4. The shared memory 2 sends the data to the processors 10a, 10b and the memories 11a and 11b. The comparators 13a and 13b compare the addresses and the data sent from the processors 10a, 10b, the memories 11a, 11b and the shared memory 2 and detect errors.
FIG. 9 is a block diagram of a conventional information processing apparatus disclosed in the Japanese patent publication No. 59-4054. In the figure, numerals 1-1 to 1-n and 3 to 4 are the same as those in FIG. 7. 5 is a fault monitor circuit for monitoring all processor modules. 6 is a private line by which the processor module 1 communicates with the fault monitor circuit 5. The fault monitor circuit 5 comprises a monitoring counter. Each processor module reads out periodically the fault monitor circuit 5 and steps up the content of the counter. Another processor module reads out the result of the fault monitor circuit 5 at a longer period than the above count up period. If the read out value is equal to the previous read out value, it is judged that there occurred a fault in the corresponding processor module.
As described above, in the conventional information processor, since the processors compared are mounted on the separate board, the delay time increases by providing many buffers between the processors and the comparators, respectively, and by the longer distances between the boards. Since it is very difficult to shorten the clock period for the above reason, a problem arises that the high operating frequency and high speed operation can not be obtained. Also since the comparators and the bus interfaces are duplicated, there arises another problem that the hardware becomes very large.
In the other conventional information processing apparatus shown in FIG. 9, the fault monitor circuit must be supplied in the center of the system. In this case, since the traffic used for detecting the fault occurs for every processor module, there arises another problem that the private line must be provided in the system.
It is an object of the present invention to provide an information processing apparatus for detecting errors of the high speed processors by using less hardware.
It is another object of the present invention to provide an information processing apparatus for detecting faults of the other processors by using a few bus loads.